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ABHINAV M - FPGA developer

ABHINAV M

This talent has passed a rigorous process of technical and soft skills interviews, system design tests, background checks, onboarding exams, and has successfully completed technical and soft skills challenges, or has demonstrated their capabilities through on-platform work.
FPGA Engineer Preferred Title
$15.00 /hr $ 20.0K /yr Hourly Rate and Yearly Salary
Overview Experiences Qualifications
Overview
Basic Summary
LD Talent History
  • Average Response Time 0.0 hours
  • Project Completion Rate 2/4
  • Interview Acceptance Rate 4/6
  • Timezone Overlap 7h PST, 56h UTC
Vetting Summary
  • No. of Onboarding MCQs Completed 3
  • Post Onboarding Exam (STEM, Soft Skills) Passed
  • Phone Number Verified
  • More details
Talent's Devices
  • Desktop Mac・Linux
  • Phone Android
General
  • Member Since Jul 10, 2025
  • Profile Last Updated Jul 11, 2025
  • Last Activity July 13, 2025, 12:36 p.m. UTC
  • Location India
  • Current Status Student
Profile Summary
I have experiencce in algorithm development and implementation on FPGAs for high performance, low latency applications.
Skills
Total Experience: 2 years
  • FPGA (2E, 2Y)

    2 experiences, across 2 years
  • VHDL (2Y)

    2 years of experience
  • C++ (2Y)

    2 years of experience
  • Python

  • Machine learning

  • Tensorflow

Weekly Availability
Timezone Overlap with 06 - 21 per Week: 7h PST, 56h UTC
Day
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
UTC
06 - 14
06 - 14
06 - 14
06 - 14
06 - 14
06 - 14
06 - 14
PST
23 - 07
23 - 07
23 - 07
23 - 07
23 - 07
23 - 07
23 - 07
Experience
Student
Course Project
Jul 2024 - Jun 2025
CERN Company
Research Industry
Project: Design and FPGA Implementation of the Barrel Calorimeter Trigger Algorithms for the High Luminosity LHC
  • VHDL
  • C++
  • FPGA
  • Developed resource efficient algorithms in C++ for FPGA implementaion
  • Gained expertise in digital logic design with VHDL
Website Links
  • https://repository.cern/records/ss38g-m7t46
Student
Course Project
Jan 2024 - Jun 2024
University of Hyderabad Company
Research Industry
Project: Implementation of Deep Learning Models on FPGA for BIB subtraction in Muon Collider
  • Python
  • FPGA
  • Machine learning
  • Tensorflow
  • Developed efficient Neural Networks using Tensorflow, Python and HLS4ML to distinguish background from signal
  • Implemented Machine Learning models on FPGA using HLS4ML and Xilinx Vivado
Website Links
  • https://agenda.hep.wisc.edu/event/2200/attachments/9677/12028/11_finalrpt_mucolml.pdf
Qualifications
Education
University of Kerala
Jun 2018 - May 2021
B.Sc. (Physics and Computer Applications)
Central University of Punjab
Aug 2021 - Jun 2023
M.Sc. (Physics)
University of Hyderabad
Aug 2023 - Jul 2025
M.Tech. (Microelectronics and VLSI Design)
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